Class: HDLRuby::High::Case

Inherits:
Low::Case show all
Includes:
HStatement
Defined in:
lib/HDLRuby/hruby_high.rb,
lib/HDLRuby/hruby_rsim.rb,
lib/HDLRuby/hruby_rsim.rb,
lib/HDLRuby/hruby_rcsim.rb,
lib/HDLRuby/hruby_rsim_vcd.rb

Overview

Enhance the Case class with VCD support.

Constant Summary collapse

High = 
HDLRuby::High

Constants included from Low::Low2Symbol

Low::Low2Symbol::Low2SymbolPrefix, Low::Low2Symbol::Low2SymbolTable, Low::Low2Symbol::Symbol2LowTable

Instance Attribute Summary collapse

Attributes inherited from Low::Case

#default, #value

Attributes included from Low::Hparent

#parent

Instance Method Summary collapse

Methods included from HStatement

#hif

Methods inherited from Low::Case

#add_when, #blocks2seq!, #boolean_in_assign2select!, #casts_without_expression!, #clone, #delete_related!, #delete_unless!, #delete_when!, #each_block, #each_block_deep, #each_deep, #each_node, #each_node_deep, #each_statement, #each_statement_deep, #each_when, #eql?, #explicit_types!, #extract_declares!, #extract_selects!, #hash, #map_nodes!, #map_whens!, #mix?, #par_in_seq2seq!, #replace_expressions!, #replace_names!, #set_default!, #set_value!, #signal2subs!, #to_c, #to_ch, #to_hdr, #to_high, #to_seq!, #to_upper_space!, #to_verilog, #to_vhdl, #use_name?, #with_var

Methods inherited from Low::Statement

#add_blocks_code, #add_make_block, #behavior, #block, #blocks2seq!, #break_types!, #clone, #delete_related!, #delete_unless!, #each_deep, #each_statement, #eql?, #explicit_types!, #extract_declares!, #hash, #mix?, #par_in_seq2seq!, #parent_system, #replace_expressions!, #replace_names!, #scope, #to_c, #to_ch, #to_hdr, #to_high, #to_seq!, #to_upper_space!, #to_vhdl, #top_block, #top_scope, #use_name?, #with_boolean!

Methods included from Low::Low2Symbol

#to_sym

Methods included from Low::Hparent

#hierarchy, #no_parent!, #scope

Constructor Details

#initialize(value) ⇒ Case

Creates a new case statement with a +value+ that decides which block to execute.



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# File 'lib/HDLRuby/hruby_high.rb', line 2623

def initialize(value)
    # Create the yes block.
    super(value.to_expr)
end

Instance Attribute Details

#rcstatement ⇒ Object (readonly)

Returns the value of attribute rcstatement.



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# File 'lib/HDLRuby/hruby_rcsim.rb', line 607

def rcstatement
  @rcstatement
end

Instance Method Details

#execute(mode) ⇒ Object

Executes the statement.



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# File 'lib/HDLRuby/hruby_rsim.rb', line 734

def execute(mode)
    unless self.each_when.find do |wh|
        if wh.match.eql?(self.value.execute(mode)) then
            wh.statement.execute(mode)
            return
        end
    end
    self.default.execute(mode) if self.default
    end
end

#fullname ⇒ Object

Returns the name of the signal with its hierarchy.



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# File 'lib/HDLRuby/hruby_rsim.rb', line 900

def fullname
    return self.parent.fullname
end

#get_vars_with_fullname(vars_with_fullname = {}) ⇒ Object

Gets the VCD variables with their long name.



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# File 'lib/HDLRuby/hruby_rsim_vcd.rb', line 519

def get_vars_with_fullname(vars_with_fullname = {})
    # Recurse on each when.
    self.each_when do |w|
        w.statement.get_vars_with_fullname(vars_with_fullname)
    end
    # Recurse on the default if any.
    self.default.get_vars_with_fullname(vars_with_fullname) if self.default
    return vars_with_fullname
end

#get_vars_with_idstr(vars_with_idstr = {}) ⇒ Object

Gets the VCD variables with their id string.



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# File 'lib/HDLRuby/hruby_rsim_vcd.rb', line 530

def get_vars_with_idstr(vars_with_idstr = {})
    # Recurse on each when.
    self.each_when do |w|
        w.statement.get_vars_with_idstr(vars_with_idstr)
    end
    # Recurse on the default if any.
    self.default.get_vars_with_idstr(vars_with_idstr) if self.default
    return vars_with_idstr
end

#helse(mode = nil, &ruby_block) ⇒ Object

Sets the block executed in +mode+ when there were no match to the block generated by the execution of +ruby_block+.

Can only be used once.



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# File 'lib/HDLRuby/hruby_high.rb', line 2645

def helse(mode = nil, &ruby_block)
    # Ensure there is a block.
    ruby_block = proc {} unless block_given?
    # Create the nu block if required
    default_block = High.make_block(mode,&ruby_block)
    # Sets the default block.
    self.default = default_block
end

#hwhen(match, mode = nil, &ruby_block) ⇒ Object

Sets the block executed in +mode+ when the value matches +match+. The block is generated by the execution of +ruby_block+.

Can only be used once for the given +match+.



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# File 'lib/HDLRuby/hruby_high.rb', line 2632

def hwhen(match, mode = nil, &ruby_block)
    # Ensure there is a block.
    ruby_block = proc {} unless block_given?
    # Create the nu block if required
    when_block = High.make_block(mode,&ruby_block)
    # Adds the case.
    self.add_when(When.new(match.to_expr,when_block))
end

#init_sim(systemT) ⇒ Object

Initialize the simulation for system +systemT+.



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# File 'lib/HDLRuby/hruby_rsim.rb', line 728

def init_sim(systemT)
    self.each_when { |wh| wh.init_sim(systemT) }
    self.default.init_sim(systemT) if self.default
end

#show_hierarchy(vcdout) ⇒ Object

Shows the hierarchy of the variables.



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# File 'lib/HDLRuby/hruby_rsim_vcd.rb', line 509

def show_hierarchy(vcdout)
    # Recurse on each when.
    self.each_when do |w|
        w.statement.show_hierarchy(vcdout)
    end
    # Recurse on the default if any.
    self.default.show_hierarchy(vcdout) if self.default
end

#to_low ⇒ Object

Converts the case to HDLRuby::Low.



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# File 'lib/HDLRuby/hruby_high.rb', line 2655

def to_low
    # Create the low level case.
    caseL = HDLRuby::Low::Case.new(@value.to_low)
    # # For debugging: set the source high object 
    # caseL.properties[:low2high] = self.hdr_id
    # self.properties[:high2low] = caseL
    # Add each when case.
    self.each_when do |w|
        caseL.add_when(w.to_low)
    end
    # Add the default if any.
    if self.default then
        caseL.default = self.default.to_low
    end
    return caseL
end

#to_rcsim ⇒ Object

Generate the C description of the hardware case.



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# File 'lib/HDLRuby/hruby_rcsim.rb', line 610

def to_rcsim
    # Create the hardware case C object.
    @rcstatement = RCSim.rcsim_make_hcase(self.value.to_rcsim,
                            self.default ? self.default.to_rcsim : nil)

    # Add the hardware whens.
    rcsim_matches = self.each_when.map {|wh| wh.match.to_rcsim }
    rcsim_stmnts = self.each_when.map {|wh| wh.statement.to_rcsim }
    if rcsim_matches.any? then
        RCSim.rcsim_add_hcase_whens(@rcstatement,rcsim_matches,
                                    rcsim_stmnts)
    end

    return @rcstatement
end