Class: CPUSimu

Inherits:
CPU
  • Object
show all
Defined in:
lib/HDLRuby/hdr_samples/sw_encrypt_cpusim_bench.rb

Overview

Simulates an 8-bit data 8-bit address CPU

Instance Attribute Summary

Attributes inherited from CPU

#abus, #ack, #allocator, #clk, #dbus, #req, #rst, #rwb

Instance Method Summary collapse

Methods inherited from CPU

#connect, #controller

Constructor Details

#initialize(clk, rst) ⇒ CPUSimu

Creates a new CPU simulator.



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# File 'lib/HDLRuby/hdr_samples/sw_encrypt_cpusim_bench.rb', line 124

def initialize(clk,rst)
    super(8,8,clk,rst)

    # The read and write control signals.
    @read_action  = inner(HDLRuby.uniq_name)
    @write_action = inner(HDLRuby.uniq_name)
    @value        = [8].inner(HDLRuby.uniq_name)

    # The CPU simulator code.
    this = self
    read_action,write_action = @read_action, @write_action
    value = @value
    par(this.posedge) do
        hif(this.rst) do
            read_action <= 0
            write_action <= 0
        end
        helse do
            hif(read_action) do
                this.hw_read(this.target,value) do
                    read_action <= 0
                end
            end
            helsif(write_action) do
                this.hw_write(this.target,write_value) do
                    write_action <= 0
                end
            end
        end
    end

    # The runtime code.
    code c: [
"unsigned char mem_read(unsigned char addr) {
unsigned char res;
write8(1,",@read_action,");
wait_cond8(0,",@read_action,");
return read8(",@value,");
}

void mem_write(unsigned char val, unsigned char addr) {
unsigned char res;
write8(1,",@write_action,");
write8(val,",@value,");
wait_cond8(0,",@write_action,");
}
"], h:
"extern unsigned char mem_read(unsigned char addr);
extern void mem_write(unsigned char val, unsigned char addr);
"
end

Instance Method Details

#hw_read ⇒ Object

Read and write are overwritten, save them before.



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# File 'lib/HDLRuby/hdr_samples/sw_encrypt_cpusim_bench.rb', line 119

alias_method :hw_read, :read

#hw_write ⇒ Object 



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# File 'lib/HDLRuby/hdr_samples/sw_encrypt_cpusim_bench.rb', line 120

alias_method :hw_write, :write

#read(code, sig) ⇒ Object

Generates a read of signal +sig+.



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# File 'lib/HDLRuby/hdr_samples/sw_encrypt_cpusim_bench.rb', line 179

def read(code,sig)
    # Generate the resulting SW access.
    return ["mem_read(",code,"0x#{self.allocator.get(sig).to_s(16)})"]
end

#write(val, sig) ⇒ Object

Generates a write of +val+ to signal +sig+.



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# File 'lib/HDLRuby/hdr_samples/sw_encrypt_cpusim_bench.rb', line 185

def write(val,sig)
    # Generate the resulting SW access.
    return ["mem_write(,",code,",#{val},#{self.allocator.get(sig).to_s(16)})"]
end