Class: HDLRuby::High::TimeRepeat

Inherits:
Low::TimeRepeat show all
Includes:
HStatement
Defined in:
lib/HDLRuby/hruby_high.rb,
lib/HDLRuby/hruby_rsim.rb,
lib/HDLRuby/hruby_rcsim.rb,
lib/HDLRuby/hruby_rsim_vcd.rb,
lib/HDLRuby/hruby_rsim_vcd.rb

Overview

Enhance the TimeRepeat class with VCD support.

Constant Summary

Constants included from Low::Low2Symbol

Low::Low2Symbol::Low2SymbolPrefix, Low::Low2Symbol::Low2SymbolTable, Low::Low2Symbol::Symbol2LowTable

Instance Attribute Summary collapse

Attributes inherited from Low::TimeRepeat

#number, #statement

Attributes included from Low::Hparent

#parent

Instance Method Summary collapse

Methods included from HStatement

#hif

Methods inherited from Low::TimeRepeat

#blocks2seq!, #boolean_in_assign2select!, #casts_without_expression!, #clone, #each_block, #each_block_deep, #each_deep, #each_node, #each_node_deep, #each_statement_deep, #eql?, #explicit_types!, #extract_declares!, #extract_selects!, #hash, #initialize, #map_nodes!, #mix?, #process_to_vhdl, #replace_expressions!, #replace_names!, #set_delay!, #set_statement!, #to_c, #to_hdr, #to_high, #to_upper_space!, #to_verilog, #to_vhdl

Methods inherited from Low::Statement

#add_blocks_code, #add_make_block, #behavior, #block, #blocks2seq!, #break_types!, #clone, #delete_related!, #delete_unless!, #each_deep, #each_statement, #eql?, #explicit_types!, #extract_declares!, #hash, #mix?, #par_in_seq2seq!, #parent_system, #replace_expressions!, #replace_names!, #scope, #to_c, #to_ch, #to_hdr, #to_high, #to_seq!, #to_upper_space!, #to_vhdl, #top_block, #top_scope, #use_name?, #with_boolean!

Methods included from Low::Low2Symbol

#to_sym

Methods included from Low::Hparent

#hierarchy, #no_parent!, #scope

Constructor Details

This class inherits a constructor from HDLRuby::Low::TimeRepeat

Instance Attribute Details

#rcstatement ⇒ Object (readonly)

Returns the value of attribute rcstatement.



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# File 'lib/HDLRuby/hruby_rcsim.rb', line 656

def rcstatement
  @rcstatement
end

Instance Method Details

#execute(mode) ⇒ Object

Executes the statement.



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# File 'lib/HDLRuby/hruby_rsim.rb', line 777

def execute(mode)
    self.number.times { self.statement.execute(mode) }
end

#get_vars_with_fullname(vars_with_fullname = {}) ⇒ Object

Gets the VCD variables with their long name.



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# File 'lib/HDLRuby/hruby_rsim_vcd.rb', line 270

def get_vars_with_fullname(vars_with_fullname = {})
    # By default: nothing to do
end

#get_vars_with_idstr(vars_with_idstr = {}) ⇒ Object

Gets the VCD variables with their id string.



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# File 'lib/HDLRuby/hruby_rsim_vcd.rb', line 275

def get_vars_with_idstr(vars_with_idstr = {})
    # By default: nothing to do
end

#init_sim(systemT) ⇒ Object

Initialize the simulation for system +systemT+.



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# File 'lib/HDLRuby/hruby_rsim.rb', line 771

def init_sim(systemT)
    # Recurde on the statement.
    self.statement.init_sim(systemT)
end

#show_hierarchy(vcdout) ⇒ Object

Shows the hierarchy of the variables.



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# File 'lib/HDLRuby/hruby_rsim_vcd.rb', line 264

def show_hierarchy(vcdout)
    # Recurse on the statement.
    self.statement.show_hierarchy(vcdout)
end

#to_low ⇒ Object

Converts the repeat statement to HDLRuby::Low.



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# File 'lib/HDLRuby/hruby_high.rb', line 2684

def to_low
    # timeRepeatL = HDLRuby::Low::TimeRepeat.new(self.statement.to_low,
    #                                     self.delay.to_low)
    timeRepeatL = HDLRuby::Low::TimeRepeat.new(self.number,
                                               self.statement.to_low)
    # # For debugging: set the source high object 
    # timeRepeatL.properties[:low2high] = self.hdr_id
    # self.properties[:high2low] = timeRepeatL
    return timeRepeatL
end

#to_rcsim(owner = nil) ⇒ Object

Generate the C description of the hardware case. +owner+ is a link to the C description of the owner behavior if any.



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# File 'lib/HDLRuby/hruby_rcsim.rb', line 660

def to_rcsim(owner = nil)
    # Create the timeRepeat C object.
    @rcstatement = RCSim.rcsim_make_timeRepeat(self.number,
                                               self.statement.to_rcsim)

    # Sets the owner if any.
    if owner then
        RCSim.rcsim_set_owner(@rcstatement,owner)
    end

    return @rcstatement
end