Module: HDLRuby::High::BlockHierarchy

Included in:
Block, TimeBlock
Defined in:
lib/HDLRuby/hruby_rsim_vcd.rb

Overview

Module adding show_hierarchyto block objects.

Instance Method Summary collapse

Instance Method Details

#get_vars_with_fullname(vars_with_fullname = {}) ⇒ Object

Gets the VCD variables with their long name.



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# File 'lib/HDLRuby/hruby_rsim_vcd.rb', line 255

def get_vars_with_fullname(vars_with_fullname = {})
    # Adds the inner signals.
    self.each_inner do |sig|
        vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
    end
    # Recurse on the statements.
    self.each_statement do |stmnt|
        stmnt.get_vars_with_fullname(vars_with_fullname)
    end
    return vars_with_fullname
end

#show_hierarchy(vcdout) ⇒ Object

Shows the hierarchy of the variables.



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# File 'lib/HDLRuby/hruby_rsim_vcd.rb', line 229

def show_hierarchy(vcdout)
    # puts "show_hierarchy for block=#{self}"
    # Shows the current level of hierarchy if there is a name.
    ismodule = false
    unless self.name.empty?
        vcdout << "$scope module #{HDLRuby::High.vcd_name(self.name)} $end\n"
        ismodule = true
    end
    # Shows the inner signals.
    self.each_inner do |sig|
        # puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
        vcdout << "$var wire #{sig.type.width} "
        vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
        vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
    end
    # Recurse on the statements
    self.each_statement do |stmnt|
        stmnt.show_hierarchy(vcdout)
    end
    # Close the current level of hierarchy if there is a name.
    if ismodule then
        vcdout << "$upscope $end\n"
    end
end