Module: HDLRuby::High::SimSignal

Included in:
SignalC, SignalI
Defined in:
lib/HDLRuby/hruby_rsim.rb,
lib/HDLRuby/hruby_rsim_vcd.rb

Overview

Enhance the signals class with VCD support.

Instance Attribute Summary collapse

Instance Method Summary collapse

Instance Attribute Details

#c_value ⇒ Object

Access the current and future value.



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# File 'lib/HDLRuby/hruby_rsim.rb', line 493

def c_value
  @c_value
end

#f_value ⇒ Object

Access the current and future value.



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# File 'lib/HDLRuby/hruby_rsim.rb', line 493

def f_value
  @f_value
end

Instance Method Details

#add_anyedge(beh) ⇒ Object

Adds behavior +beh+ activated on a any edge of the signal.



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# File 'lib/HDLRuby/hruby_rsim.rb', line 536

def add_anyedge(beh)
    # Recurse on the sub signals.
    self.each_signal {|sig| sig.add_anyedge(beh) }
    # Apply on current signal.
    @anyedge_behaviors ||= []
    @anyedge_behaviors << beh
end

#add_negedge(beh) ⇒ Object

Adds behavior +beh+ activated on a negative edge of the signal.



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# File 'lib/HDLRuby/hruby_rsim.rb', line 527

def add_negedge(beh)
    # Recurse on the sub signals.
    self.each_signal {|sig| sig.add_negedge(beh) }
    # Apply on current signal.
    @negedge_behaviors ||= []
    @negedge_behaviors << beh
end

#add_posedge(beh) ⇒ Object

Adds behavior +beh+ activated on a positive edge of the signal.



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# File 'lib/HDLRuby/hruby_rsim.rb', line 518

def add_posedge(beh)
    # Recurse on the sub signals.
    self.each_signal {|sig| sig.add_posedge(beh) }
    # Apply on current signal.
    @posedge_behaviors ||= []
    @posedge_behaviors << beh
end

#assign(mode, value) ⇒ Object

Assigns +value+ the the reference.



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# File 'lib/HDLRuby/hruby_rsim.rb', line 571

def assign(mode,value)
    # Set the next value.
    @f_value = value
    # Set the mode.
    @mode = mode
    # puts "assign #{value.content} (#{value.content.class}) with self.type.width=#{self.type.width} while value.type.width=#{value.type.width}" if self.name.to_s.include?("xnor")
    @f_value = value.cast(self.type) # Cast not always inserted by HDLRuby normally
end

#assign_at(mode, value, index) ⇒ Object

Assigns +value+ at +index+ (integer or range).



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# File 'lib/HDLRuby/hruby_rsim.rb', line 581

def assign_at(mode,value,index)
    # @f_value = @f_value.assign_at(mode,value,index)
    # Sets the next value.
    if (@f_value.equal?(@c_value)) then
        # Need to duplicate @f_value to avoid side effect.
        @f_value = Value.new(@f_value.type,@f_value.content.clone)
    end
    @f_value[index] = value
    # Sets the mode
    @mode = mode
end

#each_anyedge(&ruby_block) ⇒ Object

Iterates over the behaviors activated on any edge.



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# File 'lib/HDLRuby/hruby_rsim.rb', line 557

def each_anyedge(&ruby_block)
    @anyedge_behaviors ||= []
    @anyedge_behaviors.each(&ruby_block)
end

#each_negedge(&ruby_block) ⇒ Object

Iterates over the behaviors activated on a negative edge.



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# File 'lib/HDLRuby/hruby_rsim.rb', line 551

def each_negedge(&ruby_block)
    @negedge_behaviors ||= []
    @negedge_behaviors.each(&ruby_block)
end

#each_posedge(&ruby_block) ⇒ Object

Iterates over the behaviors activated on a positive edge.



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# File 'lib/HDLRuby/hruby_rsim.rb', line 545

def each_posedge(&ruby_block)
    @posedge_behaviors ||= []
    @posedge_behaviors.each(&ruby_block)
end

#execute(mode) ⇒ Object

Execute the expression.



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# File 'lib/HDLRuby/hruby_rsim.rb', line 564

def execute(mode)
    # puts "Executing signal=#{self.fullname} in mode=#{mode}  with c_value=#{self.c_value} and f_value=#{self.f_value}"
    return @mode == :seq ? self.f_value : self.c_value
    # return @mode == :seq || mode == :seq ? self.f_value : self.c_value
end

#fullname ⇒ Object

Returns the name of the signal with its hierarchy.



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# File 'lib/HDLRuby/hruby_rsim.rb', line 596

def fullname
    @fullname ||= self.parent.fullname + ":" + self.name.to_s
    return @fullname
end

#get_vars_with_fullname(vars_with_fullname = {}) ⇒ Object

Gets the VCD variables with their long name.



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# File 'lib/HDLRuby/hruby_rsim_vcd.rb', line 275

def get_vars_with_fullname(vars_with_fullname = {})
    if self.each_signal.any? then
        # There are sub signals, recurse on them.
        self.each_signal do |sig|
            sig.get_vars_with_fullname(vars_with_fullname)
        end
    else
        # No add the current signal.
        vars_with_fullname[self] = HDLRuby::High.vcd_name(self.fullname)
    end
    return vars_with_full_name
end

#get_vars_with_idstr(vars_with_idstr = {}) ⇒ Object

Gets the VCD variables with their id string.



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# File 'lib/HDLRuby/hruby_rsim_vcd.rb', line 289

def get_vars_with_idstr(vars_with_idstr = {})
    if self.each_signal.any? then
        # There are sub signals, recurse on them.
        self.each_signal do |sig|
            sig.get_vars_with_idstr(vars_with_idstr)
        end
    else
        # No add the current signal.
        vars_with_idstr[self] = HDLRuby::High.vcd_idstr(self)
    end
    return vars_with_idstr
end

#init_sim(systemT) ⇒ Object

Initialize the simulation for +systemT+



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# File 'lib/HDLRuby/hruby_rsim.rb', line 496

def init_sim(systemT)
    # Recurse on the sub signals if any.
    if self.each_signal.any? then
        self.each_signal {|sig| sig.init_sim(systemT) }
        return
    end
    # No sub signal, really initialize the current signal.
    if self.value then
        @c_value = self.value.execute(:par).to_value
        @f_value = @c_value.to_value
        # puts "init signal value at=#{@c_value.to_bstr}"
        # The signal is considered active.
        systemT.add_sig_active(self)
    else
        # @c_value = Value.new(self.type,"x" * self.type.width)
        # @f_value = Value.new(self.type,"x" * self.type.width)
        @c_value = Value.new(self.type,"x")
        @f_value = Value.new(self.type,"x")
    end
end

#show_hierarchy(vcdout) ⇒ Object

Shows the hierarchy of the variables.



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# File 'lib/HDLRuby/hruby_rsim_vcd.rb', line 259

def show_hierarchy(vcdout)
    # puts "show_hierarcy for signal=#{self.name}"
    if self.each_signal.any? then
        # The signal is hierarchical, recurse on the sub signals.
        vcdout << "$scope module #{HDLRuby::High.vcd_name(self.name)} $end\n"
        self.each_signal { |sig| sig.show_hierarchy(vcdout) }
        vcdout << "$upscope $end\n"
    else
        # This is a signal to show.
        vcdout << "$var wire #{self.type.width} "
        vcdout << "#{HDLRuby::High.vcd_idstr(self)} "
        vcdout << "#{HDLRuby::High.vcd_name(self.name)} $end\n"
    end
end