Module: HDLRuby::High::BlockHierarchy

Included in:
Block, TimeBlock
Defined in:
lib/HDLRuby/hruby_rsim_vcd.rb

Overview

Module adding show_hierarchyto block objects.

Instance Method Summary collapse

Instance Method Details

#get_vars_with_fullname(vars_with_fullname = {}) ⇒ Object

Gets the VCD variables with their long name.



412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
 
# File 'lib/HDLRuby/hruby_rsim_vcd.rb', line 412

def get_vars_with_fullname(vars_with_fullname = {})
    # # Adds the inner signals.
    # self.each_inner do |sig|
    #     vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
    # end
    # Recurse on the inner signals.
    self.each_inner do |sig|
        sig.get_vars_with_fullname(vars_with_fullname)
        # vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
    end
    # Recurse on the statements.
    self.each_statement do |stmnt|
        stmnt.get_vars_with_fullname(vars_with_fullname)
    end
    return vars_with_fullname
end

#get_vars_with_idstr(vars_with_idstr = {}) ⇒ Object

Gets the VCD variables with their id string.



430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
 
# File 'lib/HDLRuby/hruby_rsim_vcd.rb', line 430

def get_vars_with_idstr(vars_with_idstr = {})
    # # Adds the inner signals.
    # self.each_inner do |sig|
    #     vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
    # end
    # Recurse on the inner signals.
    self.each_inner do |sig|
        sif.get_vars_with_idstr(vars_with_idstr)
    end
    # Recurse on the statements.
    self.each_statement do |stmnt|
        stmnt.get_vars_with_idstr(vars_with_idstr)
    end
    return vars_with_idstr
end

#show_hierarchy(vcdout) ⇒ Object

Shows the hierarchy of the variables.



384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
 
# File 'lib/HDLRuby/hruby_rsim_vcd.rb', line 384

def show_hierarchy(vcdout)
    # puts "show_hierarchy for block=#{self}"
    # Shows the current level of hierarchy if there is a name.
    ismodule = false
    unless self.name.empty?
        vcdout << "$scope module #{HDLRuby::High.vcd_name(self.name)} $end\n"
        ismodule = true
    end
    # Shows the inner signals.
    self.each_inner do |sig|
        sig.show_hierarchy(vcdout)
        # # puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
        # vcdout << "$var wire #{sig.type.width} "
        # # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
        # vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
        # vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
    end
    # Recurse on the statements
    self.each_statement do |stmnt|
        stmnt.show_hierarchy(vcdout)
    end
    # Close the current level of hierarchy if there is a name.
    if ismodule then
        vcdout << "$upscope $end\n"
    end
end